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Memory access

  • February 25, 2026
  • 3 replies
  • 67 views

Hello, 

I would like to use the Metis AIPU to perform micro benchmarks, so very simple operations on which i would have the maximum control. Therefore i was wondering if there is a way to read and write for example in the cores’ L1 memory “manually”? For the moment i couldn’t find any of these, the closest being the DmaBufAllocator but i would guess it is not directly related to the core itself?

 

Thank you very much 

Best answer by Spanner

Great question ​@MArio ! Yeah, I don’t think DmaBufAllocator is the right tool here, as you say. 

L1 memory is internal to each core and is only accessible from code executing on that core, as I understand it. There's no API in the current Voyager SDK to read/write L1 directly from the host. The memory regions you can work with at the application level are host RAM and device DDR (via DMA buffers), with L2 and L1 managed implicitly by the compiled kernels.

For micro-benchmarking at that level, you'd need a custom kernel running on the AICore itself, which I don’t think is currently supported. But I believe there’s work going on to provide more access in this aspect, for exactly the reasons you mentioned.

What kind of benchmarking are you trying to run, out of interest?

3 replies

Spanner
Axelera Team
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  • Axelera Team
  • Answer
  • March 3, 2026

Great question ​@MArio ! Yeah, I don’t think DmaBufAllocator is the right tool here, as you say. 

L1 memory is internal to each core and is only accessible from code executing on that core, as I understand it. There's no API in the current Voyager SDK to read/write L1 directly from the host. The memory regions you can work with at the application level are host RAM and device DDR (via DMA buffers), with L2 and L1 managed implicitly by the compiled kernels.

For micro-benchmarking at that level, you'd need a custom kernel running on the AICore itself, which I don’t think is currently supported. But I believe there’s work going on to provide more access in this aspect, for exactly the reasons you mentioned.

What kind of benchmarking are you trying to run, out of interest?


  • Author
  • Ensign
  • March 4, 2026

Hello ​@Spanner , thank you very much for your answer!

I am trying to perform different benchmarks to see the behaviour of the system under stress, and this one would be a memory benchmark


  • Axelera Team
  • March 20, 2026

@MArio Just like you can not manually access the L1 cache of a CPU, you can not have that level of control here either. Speaking of the behaviour, what behaviour is of your interest? What applications or use cases require such behaviour? I am all ears.