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Hi, I have a custom U-Net model with MobileNetV2 encoder running on the Axelera portenta with voyager v1.4.0. I’ve based my code for inference on the axruntime python example in the Voyager github repository, with the model being compiled by the Voyager compiler. When running inference the maximum utilization of the Metis, as shown by axmonitor, only reaches 6% on all four cores. I have tried running it with all pre-processing and post-processing commented out and a dummy input consisting of all zeroes, but utilization also did not surpass 6%. I’m wondering whether this utilization limit might be caused by the way the model is compiled, perhaps due to needing multiple iterations in the LowerTIR stage, and whether there might be more optimal compiler configs to achieve a higher utilization. I have included some logging / debug files the CLI compiler generated for an older version of my model. For my current model I’m using the API compiler but it does not generate these files, the only

I recently acquired a Metis M.2 module and was so excited to get started with it. To my horror, I installed it into a standard, modern x86 mini PC (with power disconnected, all by the books), and the system was bricked upon my first attempt to boot. At first, I thought maybe the M.2 slot on the system was not providing adequate power for the device, and to the benefit of the Metis, I decided to try another host system. HUGE mistake. The same thing happened with a LattePanda x86 SBC, confirmed to have enough power to the M-key M.2 slot. These systems are not cheap, so to say I am disappointed is an incredible understatement.  Maybe I’m just not understanding where to look for host system specs, but it doesn’t seem like this issue is warned against anywhere in your docs or on the community page here. Has anyone else had this problem? I’m down two systems, so if someone could please tell me with certainty which system I CAN reliably plug this thing into, I would be very appreciative. EDIT

We currently run the Voyager SDK + Metis AIPU on a custom Yocto image (Scarthgap 5.0.18) on x86_64 (Ryzen 5 8500G / B650M). We're migrating the base OS to Ubuntu/Debian for hardware-agnostic driver support, and want to confirm a few things before starting:Is there an officially supported/tested Ubuntu or Debian version (and kernel version range) for the Metis driver + Voyager SDK on x86_64? Do you provide a .deb package or install script for the Metis kernel driver, or does it require a manual out-of-tree module build (e.g., via dkms)? Are there any known kernel version constraints or incompatibilities (e.g., minimum/maximum kernel version, specific config options required) we should account for when picking a distro kernel package? Any existing documentation or community reference for deploying the Metis driver outside of a Yocto-based image?

SummaryOn a Metis dev system, ./deploy.py <model> fails at the compile step: it exits with RC=1 and writes nothing to stdout or stderr (captured 1>out.txt 2>err.txt → both empty), produces no log file, and no traceback. It reproduces on a trivial 27×30 model, so it is not model‑size related. The one time the compiler did emit an error (earlier run, attached earlier_pkl_memoize_PermissionError.md) it was a TVM .pkl_memoize_py3 PermissionError, which makes me suspect the current silent failure is the same TVM‑cache / working‑directory‑writability problem, now swallowed.EnvironmentHardware: Metis dev system — Portenta X8 on the board, host access via a Raspberry Pi acting as an adb relay over USB. SDK: Voyager container voyager-sdk-1.4.0, SDK at /home/ubuntu/voyager-sdk, venv /home/ubuntu/.cache/axelera/venvs/b4c581dc (Python 3.10, TVM backend). from axelera import compiler, runtime imports successfully (prints OK).What I'm deployingA single 1×1 Conv2d exported to ONNX (it imp

As the title suggests, I want to factory reset the board so that I can reinstall and setup the board from a clean state? How can I do it?

class FrameResult:image: Optional[types.Image] = Nonetensor: Optional[np.ndarray] = Nonemeta: Optional[AxMeta] = Nonestream_id: int = 0src_timestamp: int = 0sink_timestamp: int = 0render_timestamp: int = 0Could you explain when exactly these 3 timestamps are stamped? Our use case is we are trying to sync some telemetry samples with the exact moment the camera has recorded the frame. So it would be helpful to know what events trigger these timestamps.Thank you,

Will this ever be made available? I am interested in the 16gb version.   

Hi everyone — I'm Lorenco, a Rust/C++ compiler & real-time/kernel systems engineer (based in Italy), getting to know the Metis/Voyager stack.While reading axelera-driver I came across GitHub issue #4 — the use-after-free in axl_aipu_remove() on `modprobe -r metis`. It looks correctly root-caused: the MSI handlers dereference dma_va, but the devm-managed IRQs are only released after remove() returns, so a late MSI hits the freed DMA buffer (synchronize_irq() alone doesn't mask the vector). Quiescing DMA/MSI before the free would also unblock a clean S3 suspend path.Two questions:1. Is the GitHub repo the right place to send driver patches, or do you handle those through another channel?2. More broadly — I do low-level compiler/runtime/driver work and would be glad to contribute. Where's the best spot for someone outside the team to pick things up?Background, in case useful: I recently contributed a canonicalization fix to Tenstorrent's tt-mlir compiler (github.com/tenstorrent/tt-mli

Hi,I'm trying to deploy a custom classification model on the Metis AIPU using the Voyager SDK. The model includes a CBAM attention block, but it fails during quantization with a topological sort error that points to a Gemm node.To verify that the issue wasn't in my model, I inspected the ONNX graph before quantization. The CBAM block contains only MatMul operations and no Gemm nodes. The only Gemm nodes in the model are in the final classifier head. Because of that, the Gemm mentioned in the error doesn't actually exist in the exported ONNX graph. It looks like the compiler is creating it internally during a MatMul to Gemm fusion pass, and somehow placing it before the node that produces one of its inputs.The graph pattern that seems to trigger this consists of two parallel MatMul branches that merge into a shared Add operation. As far as I know, this is a standard CBAM channel attention structure and not an unusual graph layout.Is this a known limitation of the compiler when handling

Hey everyone,I am evaluating the Metis lineup for an edge AI project and have a specific question about multi-card architecture that I haven't found a definitive answer to in the docs or SDK references.What I understand is supported today: The Voyager SDK detects multiple Metis cards in a single host. Each card runs its own independent inference pipeline. A real-world surveillance example shows three 4-chip PCIe cards running five primary models + one secondary model in parallel across 48 AIPU cores. My question: Is there any current or planned SDK support for splitting a single neural network across multiple Metis cards (e.g., layer sharding or tensor parallelism across two M.2 cards)? Or is the architecture strictly "one model must fit entirely within a single card's memory and AIPU"?Context for my use case: I am looking at a host with dual M.2 slots (e.g., Radxa Orion O6N) and weighing whether two standard Metis M.2 cards could act as a unified 2-GB / 428-TOPS accelerator for a

I received my Metis M.2 card yesterday and tried it out on Windows 11 on an ACEMAGIC F3A AMD Ryzen AI 9 HX 370 Mini PC using the instructions in https://docs.axelera.ai/sdk/user-guides/windows-setup/.  I had some troubles with the WSL part of the setup so I decided to skip that, and got to step 5 with the driver properly installed in device manager and the Axelera Windows packages installed. The axrunmodel sample returns the following output: [libaxldev.c:419] Firmware load address 0xffffffffffffffff exceeds 32-bit address space on Metis. WARNING:axelera.runtime:Failed to load runtime stage0: C:\AxeleraDevice-1.7.0\opt\axelera\device\omega\bin\start_axelera_runtime_stage0.bin [AxeleraDevice.cpp:455] Failed to get board DDR size. WARNING:axelera.runtime:Failed to get SW throttling from device metis-0:0:0 WARNING:axelera.runtime:Failed to get HW throttling from device metis-0:0:0 WARNING:axelera.runtime:Failed to get freq downscaling from device metis-0:0:0 [utils.c:264] sysctl_get_datas

Hi, when running inference on Metis M.2 on raspberry CM5 we noticed these errors occuring after couple minutes. error log: [libtriton_linux.c:531] DMABUF_METIS_XFER failed: Input/output error [AxeleraDmaBuf.cpp:222] DMA transfer failed: Input/output error [ERROR][axeShareMemoryExecute]: Dmabuf transfer failed. [ERROR][axeCommandQueueExecuteCommandListsAsync]: Level-zero memory operation failed: 0x70010001. terminate called after throwing an instance of 'std::runtime_error' what():  axr_run_model failed with Error at zeCommandQueueExecuteCommandLists(cmdqueue, n_cmdlists, cmdlists, nullptr): cmdqueue_run_cmdlists: 319: Exit with error code: 0x70010001 : ZE_RESULT_ERROR_NOT_AVAILABLE kernel errror log: axl 0001:01:00.0: DMA error WR CH0 (ctrl 0x1) setup:  Runtime: runtime-1.5.3-1 - Voyager SDK: v1.5.2 - metis-dkms: 1.4.4 - Firmware: flash version 1.5.0 - bcver 7.1

Hi I'm Zero (sudo name) I'm a reverse engineering expert. Here to learn how can I involve Ai in my work and make it more sturdy

Hello Axelera Community,I’ve been working on a project that I’m excited to share: a real-time face recognition home surveillance and attendance system using the Voyager SDK. My goal was to create a reliable system that could identify individuals from an RTSP stream and display their names accurately on-screen.I’m using a multi-model pipeline, starting with RetinaFace-Resnet50 for detection and then leveraging the FaceNet-LFW model for recognition, implemented through the face-recognition and face-recognition-with-vote components. While I've made progress, I’ve also encountered some challenges, particularly around database management and recognition accuracy. I wanted to share my approach and ask for advice from the community.My Current ApproachThe system architecture involves two main steps: Database Creation: I use the ./inference.py face-recognition faces/person/folder command to generate embeddings from images in my dataset. This creates a famous_embeddings.json file, which acts as

Subject Metis M.2 on Toradex Verdin i.MX95 enumerates over PCIe but all Axelera commands time out after (reportedly) successful firmware update; MSI interrupts never increment and board firmware version can no longer be queried Summary We are using an Axelera Metis M.2 accelerator on a Toradex Verdin i.MX95 WB on Mallow carrier. PCIe enumeration succeeds and the `metis` kernel driver binds to the endpoint, but all Axelera device commands fail to retrieve board/device information. The kernel repeatedly logs: axl 0000:01:00.0: IRQ MSI timeout (12 1) This persists with ARM SMMU passthrough enabled via `iommu.passthrough=1`. The most important observation is that the Metis MSI interrupt counters do not increment when an Axelera command is issued. The endpoint advertises MSI and the driver allocates MSI vectors, but the expected completion interrupt is never observed by Linux. Environment Host: Toradex Verdin iMX95 WB on Mallow BoardLinux 6.6.138-7.6.1-develTDX Wayland with XWayland 7.6.1-d

Hi,I have a C++ application using GStreamer on Windows that connects to a custom camera and performs preprocessing. I want to run a segmentation model on an Axelera Metis M.2 card.I installed the Windows packages and drivers successfully, but I don’t see any .lib files or clear way to link Axelera runtime directly into my C++ application on Windows.My goal is to integrate inference directly into my existing pipeline (ideally via GStreamer or better with a C++ API), rather than running a separate process.Questions:- Is native C++ integration on Windows supported (e.g., via .lib )? - What is the recommended architecture for integrating Axelera into an existing C++/GStreamer application on Windows?Thanks

Hi! My name is Salvador and I’ve been trying to integrate the Metis M.2 on a Jetson Orin NX 16GB to perform Computer vision tasks.Recently the Axelera team shared a guide to Bring up Metis M.2 on Jetson Orin, where they explain the steps required to modify the kernel to use the Metis Accelerator.For me these changes were not enough, so I had to perform additional steps to make it work, I hope this post is useful for anybody trying to accomplish the same. The following steps build upon the instructions provided by the Axelera team.Prepare the Nvidia files necessaryWe will use a host machine running Ubuntu 20.04 or 22.04 (newer versions are not compatible with some Nvidia tools) where we will run all the described process, download the kernel sources, the Jetson Sample Filesystem, and the Jetson linux toolchain, and execute the cross compilation of the linux kernel, and the flashing into the Jetson Oring NX. To install the Jetson toolchain just follow the instructions provided on the lin

Hello, i just got my m.2 card and on my AMD64 desktop workstation, the Metis M.2 AIPU does not survive an S3(suspend-to-RAM) cycle. After resume, every large DMA transfer to the cardfails permanently. Only a full cold power-cycle restores function — a warmreboot is not enough. This makes the card unusable on any normal desktop,where suspend/resume is the standard daily workflow.I narrowed this down together with Claude Opus 4.8 (Anthropic) over a detaileddebugging session. Full diagnosis below.## Hardware / Software- Host: AMD Ryzen, B850 platform, RTX 3090 in primary slot- OS: CachyOS (Arch-based), kernel 7.0.12 (Clang/LLVM-built), Secure Boot off- Metis M.2 AIPU, PCIe 0000:0c:00.0 (1f9d:1100 rev 02), Gen3 x4- Driver: axelera-driver release/v1.6 (module version 1.4.17), built with  make LLVM=1, DKMS-managed- SDK: Voyager 1.6.1 (axelera-rt / devkit), inference via distrobox/Ubuntu 24.04## Reproduction1. Cold boot. Run inference (yolo26s-coco-onnx, fakevideo) → works, ~529 fps.2. system

use the metis m.2, zed x and nvme on a jetson orin nx 16gb a condensed field guide to a real-time vision stack on the orin nx 16gb: preempt_rt kernel, axelera metis npu, zed x stereo, nvme. every section here exists in long form in the repository docs, linked throughout and listed at the end. what this isa complete recipe for taking a stock jetson orin nx 16gb and turning it into a real-time vision platform:custom preempt_rt kernel with low-jitter tuning (cyclictest avg ~3 µs on the isolated cores; max under the 100 µs gate make verify enforces. run it headless — a desktop session adds ~150 µs ipi spikes) axelera metis m.2 as the inference accelerator (in-tree driver, not oot, vermagic-safe). detection costs the jetson's gpu essentially nothing, which is the whole point stereolabs zed x via the zed link mono capture card (max9296 deserializer) nvme boot + a btrfs data partition for recordings dmabuf zero-copy pipeline (design goal: camera → isp → npu with no cpu memcpy)everything below

Hello,I am trying to compile an IBM Granite embedding model for the Metis AIPU.Current test model:ibm-granite/granite-embedding-311m-multilingual-r2https://huggingface.co/ibm-granite/granite-embedding-311m-multilingual-r2My final target model is:ibm-granite/granite-switch-4.1-3b-previewhttps://huggingface.co/ibm-granite/granite-switch-4.1-3b-previewTarget hardware and software:Metis SBC16 GB board RAM4 GB AIPUPython 3.12Voyager SDK 1.6.0I tried to compile the embedding model with `axcompile`, but it fails during quantization.Command:bashaxcompile \ --input granite_embedding_metis_work/granite_embedding_311m_static.onnx \ --config granite_embedding_metis_work/granite_embedding_metis_4gb.json \ --output granite_embedding_metis_work/axcompile_out \ --overwrite \ --dataset-len 2 \ --log-level DEBUG \ --quantize-onlyThe ONNX export succeeds.Current ONNX details:ONNX opset: 17Input: inputs_embeds [1, 128, 768]Output: embeddings [1, 768]The model reaches calibration, then fails after c

Hello everyoneI have an Axelera Metis PCIe card with the hardware setup completed, and I am planning to build a home CCTV surveillance web application. My goal is to process multiple RTSP/IP camera streams in real time using AI models such as RetinaFace for face detection, FaceNet for face recognition, and YOLOv8n ONNX for object detection. I would like to create a web dashboard where users can view live camera feeds, detect and recognize known faces, identify unknown visitors, monitor people and objects, and store detection logs and alerts. I am considering using FastAPI as the backend and a web frontend for live monitoring and management.I would like guidance on the best way to integrate these AI models with the Metis card and expose the results through APIs. Are there any recommended examples, repositories, or best practices for running multiple AI pipelines simultaneously on Metis? I am also interested in learning how other developers handle RTSP streams, face embedding databases,

For anyone building custom embedded Linux images with Yocto, there's now an official BSP layer available for Metis hardware.It’s pretty niche stuff, but if you're working on embedded systems where you need a stripped-down, customised Linux image (think industrial deployments, kiosks, dedicated edge boxes), this is for you.What's in it:The layer includes recipes for the Metis PCIe driver and the udev rules. Add it to your Yocto build, include the packages in your image, and your custom Linux will recognise and talk to Metis hardware out of the box.Currently supports Yocto 5.0 (Scarthgap), with branches for Kirkstone and Dunfell if you're on older versions.One important thing to note:The VoyagerSDK itself still doesn't run natively on Yocto yet. You'll need to run it inside a Docker container on your target system. The kernel driver runs on the host and handles the hardware communication, but inference and SDK tools happen inside the container. Just FYI 👍.Quick look at the setup:Clone t

I am integrating Axelera Metis into a yocto-based project for a customer.In their case, this is a Zynq-UltraScale+ Petalinux 2025.2 project (yocto scarthgap).I have successfully integrated the meta-axelera layerroot@zcu104-axelera-2025-2:~# lspci -vvv00:00.0 PCI bridge: Xilinx Corporation Device 9131 (prog-if 00 [Normal decode]) …01:00.0 Processing accelerators: Axelera AI Metis AIPU (rev 02) Subsystem: Axelera AI Metis AIPU (rev 02) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- D- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-- Interrupt: pin A routed to IRQ 89 Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/32 Maskable+ 64bit+