Team: Banca Semmir Ltd.
VideoDemo: https://youtube.com/@bancateknology?si=Eh64MgcAuppa4n8Q
The Engineering Challenge:
How do you fit a complete Signal Intelligence (SIGINT) command center, a deep-learning RF analyzer, and a cryptographic brute-force unit into a sealed, 25mm-thick magnesium tactical armor running on battery power? You cannot rely on traditional desktop GPUs or power-hungry servers. You must redefine edge computing using an asymmetric M.2 architecture.
The Solution: The "Big.LITTLE" Tactical AI Doctrine
For this Demo Jam, we are thrilled to unveil the intelligence pipeline of Banca Semmir V3. Our system utilizes a custom 6-slot PCIe M.2 backplane connected to a rugged Getac tactical tablet. To survive the strict thermal and power constraints of the frontline, we divided our AI workload into two distinct roles:
- The Spotter (Slot 5 - DeGirum ORCA): A low-power ASIC running continuously on just 1-3 Watts. It constantly scans raw RF data from our SDR for anomalies without draining the battery.
- The Heavyweight Analyst (Slot 6 - Axelera Metis): The absolute powerhouse of our system. It remains in an idle, power-saving state until a target is acquired.
What You Are Seeing in the Video:
In this hardware demonstration, you are looking at our custom 4K Tactical HUD paired with our live PCIe backplane prototype logic.
- Idle Phase: The left panel shows the ORCA continuously scanning the environment (UHF band) while the Axelera Metis core rests at 1% NPU utilization.
- Target Acquisition & Spike: An anomaly is isolated. Watch the system telemetry on the right: The Axelera Metis core instantly wakes up, spiking to 100% NPU load.
- Zero-Copy DMA Execution: Instead of bottlenecking the CPU, raw I/Q data is routed directly to the Axelera chip. Within seconds, Metis runs a deep-learning classification model, identifies the signal as "Encrypted Drone Telemetry," extracts the cryptographic hash, and pushes it directly to our Numato Artix UltraScale+ FPGA (Slot 2) to initiate a brute-force attack.
Progress over perfection. This is the future of mobile SIGINT
Project Title: Banca Semmir V3 - Asymmetric Edge SIGINT & AI Architecture
+3- Axelera Team
Nice build! The Big.LITTLE approach to splitting the workload between ORCA and Metis is a brilliant way to handle the power budget. Love seeing Metis used as a "sleep until needed" heavyweight like this. I did something similar (on some very different devices) recently to get a Meshtastic device to work on battery and solar!
One thing I'm curious about: for the zero-copy DMA path from the SDR to Metis, how are you routing the raw I/Q data without hitting the CPU? Is there a bridge or DMA controller sitting between the SDR and the M.2 slots, or is the Getac host handling the initial buffer setup?
Hi Spanner,
Thanks for the great feedback! You hit the nail on the head regarding the power budget. Keeping the Metis dormant until the brute-force/inference phase is critical for our strict 4-hour solid-state battery doctrine in harsh tactical environments. Glad to hear you're doing similar power-optimization work with Meshtastic!
Regarding your question about the zero-copy DMA path: We keep the Getac host entirely out of the heavy I/Q data path. Routing that massive firehose of 5 GSPS data through a host CPU would be a lethal bottleneck for our latency requirements.
Here is how we bypass the CPU completely:
The architecture relies on the Programmable Logic (PL) fabric of the XCZU47DR RFSoC. The Metis M.2 accelerator is physically integrated directly onto the SDR board via a custom 60-Pin BTB-to-M.2 PCIe Gen3 x4 expansion adapter. This makes the RFSoC the PCIe Root Complex.
We implemented a custom AXI DMA engine within the FPGA's PL side. The raw I/Q data flows from the RF-ADCs straight into the FPGA fabric. From there, the AXI DMA engine uses PCIe Peer-to-Peer (P2P) direct memory mapping to push the I/Q streams directly into the Metis card's memory address space over those 4 PCIe lanes.
The Getac host (connected via a separate 100G QSFP28/Thunderbolt 4 link running DragonOS) acts strictly as a Command & Control (C2) interface and waterfall visualizer. Zero host CPU cycles are wasted on moving the actual RF data. The SDR and the AI accelerator talk to each other in total silence on the edge.
Let me know if you want to dive deeper into the AXI configurations or the BTB60 pinout mapping!
Best regards,
Navturk (Banca Semmir V3 Lead
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