Hi there @IAK, welcome on board!
Hmm, since you’ve seen this on both the Raspberry Pi and your laptop, it might be related to the runtime environment in Docker rather than the board firmware?
First quick thing to try: can you run this command inside your Docker container and share the output?
glxinfo | grep "OpenGL renderer"
This will help confirm whether OpenGL ES is available and functioning properly, which is required for inference display on the Pi5. If it’s working, missing or misconfigured, we can go from there 
Hi @Spanner
Thanks, glad to be here!
After running the glxinfo | grep "OpenGL renderer" command inside my docker I have the following output:
⬢ nDocker] ❯ glxinfo | grep "OpenGL renderer"
OpenGL renderer string: V3D 7.1
Guess it is configured fine, isn’t it?
Ah, that’s good news! Well, not good news that you’re having an issue, but it’s good that we’ve confirmed that OpenGL is working 
Thanks for the info.
Maybe we should check that the Metis card is being recognised correctly? If you could run the following command inside the container and share the output:
axdevice
That should five us some info about its status, firmware, etc.
Hello @IAK
May I ask which RPi HAT are you using?
I also recommend you to take a look at our troubleshooting guide in https://support.axelera.ai/hc/en-us/articles/26261515755538-PCIe-Troubleshooting-Guide
Regards,
Victor
Ah, that’s good news! Well, not good news that you’re having an issue, but it’s good that we’ve confirmed that OpenGL is working Thanks for the info.
Maybe we should check that the Metis card is being recognised correctly? If you could run the following command inside the container and share the output:
axdevice
That should five us some info about its status, firmware, etc.
Facing the same issue.
Device 0: metis-1:1:0 board_type=m2 fwver='v1.2.5' clock=800MHz(0-3:800MHz) mvm=0-3:100%
using Waveshare pcie to m.2 hat
https://thepihut.com/collections/waveshare/products/pcie-to-m-2-adapter-for-raspberry-pi-5
OUTPUT OF dmesg -T
Tue May 27 14:49:08 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:49:09 2025] axl 0001:01:00.0: DMA WR CH0 queue timeout (00000000f2589e77 status 0)
aTue May 27 14:49:09 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:49:10 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:49:11 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:49:12 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:49:13 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:49:42 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:49:43 2025] axl 0001:01:00.0: DMA WR CH0 queue timeout (00000000fdc5a1e2 status 0)
aTue May 27 14:49:43 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:49:44 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:49:45 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:49:46 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:49:47 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:55:52 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:55:53 2025] axl 0001:01:00.0: DMA WR CH0 queue timeout (00000000cf307059 status 0)
aTue May 27 14:55:53 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:55:54 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:55:55 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:55:56 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:55:57 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:56:19 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:56:20 2025] axl 0001:01:00.0: DMA WR CH0 queue timeout (00000000c592c395 status 0)
aTue May 27 14:56:20 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:56:21 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:56:22 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:56:23 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:56:24 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
rTue May 27 14:58:11 2025] axl 0001:01:00.0: Unregister directory 0001:01:00.0
0Tue May 27 14:58:11 2025] axl 0001:01:00.0: Unregistered triton-1:1:0 (0 0)
0Tue May 27 14:58:11 2025] axl 0001:01:00.0: Release dma mem triton-1:1:0
nTue May 27 14:58:11 2025] pci_bus 0001:01: busn_res: 1bus 01] is released
eTue May 27 14:58:12 2025] triton: debugfs root directory triton removed
eTue May 27 14:58:13 2025] pci 0001:00:00.0: 014e4:2712] type 01 class 0x060400 PCIe Root Port
oTue May 27 14:58:13 2025] pci 0001:00:00.0: PCI bridge to Pbus 01]
[Tue May 27 14:58:13 2025] pci 0001:00:00.0: bridge window mem 0x1b80000000-0x1b82ffffff]
8Tue May 27 14:58:13 2025] pci 0001:00:00.0: PME# supported from D0 D3hot
Tue May 27 14:58:13 2025] brcm-pcie 1000110000.pcie: clkreq-mode set to safe
tTue May 27 14:58:13 2025] brcm-pcie 1000110000.pcie: link up, 8.0 GT/s PCIe x1 (!SSC)
xTue May 27 14:58:13 2025] pci 0001:01:00.0: 1f9d:1100] type 00 class 0x120000 PCIe Endpoint
Tue May 27 14:58:13 2025] pci 0001:01:00.0: BAR 0 0mem 0x1b82010000-0x1b82010fff 64bit]
fTue May 27 14:58:13 2025] pci 0001:01:00.0: BAR 2 0mem 0x1b80000000-0x1b81ffffff]
8Tue May 27 14:58:13 2025] pci 0001:01:00.0: ROM 1mem 0x00000000-0x0000ffff pref]
fTue May 27 14:58:13 2025] pci 0001:01:00.0: supports D1
pTue May 27 14:58:13 2025] pci 0001:01:00.0: PME# supported from D0 D1 D3hot
Tue May 27 14:58:13 2025] pci 0001:01:00.0: 7.876 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x1 link at 0001:00:00.0 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link)
Tue May 27 14:58:13 2025] pci 0001:00:00.0: bridge window mem 0x1b80000000-0x1b82ffffff]: assigned
Tue May 27 14:58:13 2025] pci 0001:01:00.0: BAR 2 0mem 0x1b80000000-0x1b81ffffff]: assigned
Tue May 27 14:58:13 2025] pci 0001:01:00.0: ROM 1mem 0x1b82000000-0x1b8200ffff pref]: assigned
Tue May 27 14:58:13 2025] pci 0001:01:00.0: BAR 0 0mem 0x1b82010000-0x1b82010fff 64bit]: assigned
Tue May 27 14:58:13 2025] pci 0001:00:00.0: PCI bridge to bus 01]
Tue May 27 14:58:13 2025] pci 0001:00:00.0: bridge window mem 0x1b80000000-0x1b82ffffff]
bTue May 27 14:58:13 2025] pcieport 0001:00:00.0: PME: Signaling with IRQ 39
iTue May 27 14:58:13 2025] pcieport 0001:00:00.0: AER: enabled with IRQ 39
iTue May 27 14:58:13 2025] pci 0001:01:00.0: Found target device: TRITON_OMEGA_DEVICE_ID
_Tue May 27 14:58:13 2025] pci 0001:01:00.0: Found target device: 0001:01:00.0
0Tue May 27 14:58:13 2025] pcieport 0001:00:00.0: Found bridge device: 0001:00:00.0
0Tue May 27 14:58:13 2025] pcieport 0001:00:00.0: Bridge window: mem 0x1b80000000-0x1b82ffffff]
bTue May 27 14:58:13 2025] pcieport 0001:00:00.0: Decoded memory behind bridge: 1b80000000-1b82ffffff
1Tue May 27 14:58:13 2025] pcieport 0001:00:00.0: Memory behind bridge is sufficient. Skipping reset.
iTue May 27 14:58:13 2025] triton: root directory for triton
fTue May 27 14:58:13 2025] axl 0001:01:00.0: MSI registered 32 (32)
eTue May 27 14:58:13 2025] axl 0001:01:00.0: irq vec number 186
nTue May 27 14:58:13 2025] axl 0001:01:00.0: Register directory 0001:01:00.0
0Tue May 27 14:58:13 2025] Triton Linux Driver, version 0.07.16, init OK
6Tue May 27 15:02:24 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
Tue May 27 15:02:25 2025] axl 0001:01:00.0: DMA WR CH0 queue timeout (000000001768cf1f status 0)
Tue May 27 15:02:25 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
Tue May 27 15:02:26 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
Tue May 27 15:02:27 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
Tue May 27 15:02:28 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
Tue May 27 15:02:29 2025] axl 0001:01:00.0: DMA RD CH0 timeout (irq 4, ctrl 0x3)
Tue May 27 15:03:54 2025] axl 0001:01:00.0: Unregister directory 0001:01:00.0
0Tue May 27 15:03:54 2025] axl 0001:01:00.0: Unregistered triton-1:1:0 (0 0)
:Tue May 27 15:03:54 2025] axl 0001:01:00.0: Release dma mem triton-1:1:0
iTue May 27 15:03:54 2025] pci_bus 0001:01: busn_res: 1bus 01] is released
sTue May 27 15:03:55 2025] triton: debugfs root directory triton removed
nTue May 27 15:03:56 2025] pci 0001:00:00.0: c14e4:2712] type 01 class 0x060400 PCIe Root Port
eTue May 27 15:03:56 2025] pci 0001:00:00.0: PCI bridge to 0bus 01]
tTue May 27 15:03:56 2025] pci 0001:00:00.0: bridge window mem 0x1b80000000-0x1b82ffffff]
xTue May 27 15:03:56 2025] pci 0001:00:00.0: PME# supported from D0 D3hot
rTue May 27 15:03:56 2025] brcm-pcie 1000110000.pcie: clkreq-mode set to safe
Tue May 27 15:03:56 2025] brcm-pcie 1000110000.pcie: link up, 8.0 GT/s PCIe x1 (!SSC)
ITue May 27 15:03:56 2025] pci 0001:01:00.0: p1f9d:1100] type 00 class 0x120000 PCIe Endpoint
CTue May 27 15:03:56 2025] pci 0001:01:00.0: BAR 0 0mem 0x1b82010000-0x1b82010fff 64bit]
1Tue May 27 15:03:56 2025] pci 0001:01:00.0: BAR 2 0mem 0x1b80000000-0x1b81ffffff]
xTue May 27 15:03:56 2025] pci 0001:01:00.0: ROM 0mem 0x00000000-0x0000ffff pref]
0Tue May 27 15:03:56 2025] pci 0001:01:00.0: supports D1
Tue May 27 15:03:56 2025] pci 0001:01:00.0: PME# supported from D0 D1 D3hot
Tue May 27 15:03:56 2025] pci 0001:01:00.0: 7.876 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x1 link at 0001:00:00.0 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link)
CTue May 27 15:03:56 2025] pci 0001:00:00.0: bridge window .mem 0x1b80000000-0x1b82ffffff]: assigned
fTue May 27 15:03:56 2025] pci 0001:01:00.0: BAR 2 0mem 0x1b80000000-0x1b81ffffff]: assigned
fTue May 27 15:03:56 2025] pci 0001:01:00.0: ROM 0mem 0x1b82000000-0x1b8200ffff pref]: assigned
fTue May 27 15:03:56 2025] pci 0001:01:00.0: BAR 0 0mem 0x1b82010000-0x1b82010fff 64bit]: assigned
tTue May 27 15:03:56 2025] pci 0001:00:00.0: PCI bridge to .bus 01]
Tue May 27 15:03:56 2025] pci 0001:00:00.0: bridge window :mem 0x1b80000000-0x1b82ffffff]
0Tue May 27 15:03:56 2025] pcieport 0001:00:00.0: PME: Signaling with IRQ 39
gTue May 27 15:03:56 2025] pcieport 0001:00:00.0: AER: enabled with IRQ 39
dTue May 27 15:03:56 2025] pci 0001:01:00.0: Found target device: TRITON_OMEGA_DEVICE_ID
ETue May 27 15:03:56 2025] pci 0001:01:00.0: Found target device: 0001:01:00.0
Tue May 27 15:03:56 2025] pcieport 0001:00:00.0: Found bridge device: 0001:00:00.0
Tue May 27 15:03:56 2025] pcieport 0001:00:00.0: Bridge window: .mem 0x1b80000000-0x1b82ffffff]
0Tue May 27 15:03:56 2025] pcieport 0001:00:00.0: Decoded memory behind bridge: 1b80000000-1b82ffffff
0Tue May 27 15:03:56 2025] pcieport 0001:00:00.0: Memory behind bridge is sufficient. Skipping reset.
iTue May 27 15:03:56 2025] triton: root directory for triton
rTue May 27 15:03:56 2025] axl 0001:01:00.0: MSI registered 32 (32)
tTue May 27 15:03:56 2025] axl 0001:01:00.0: irq vec number 186
eTue May 27 15:03:56 2025] axl 0001:01:00.0: Register directory 0001:01:00.0
Tue May 27 15:03:56 2025] Triton Linux Driver, version 0.07.16, init OK
Hello @dev.manek ,
Did you follow the guide in https://www.waveshare.com/wiki/PCIe_TO_M.2_HAT+ ?
Specifically this is very important:
1: Enable PCIe Interface:
The PCIe interface is not enabled by default on PI5B. To enable it, add the following configuration in /boot/firmware/config.txt:dtparam=pciex1
2: PCIE is gen2 by default, if you need to enable PCIE gen3, add it in /boot/firmware/config.txt:
dtparam=pciex1_gen=3
Please enable PCIE gen3 as described in step 2.
At the moment, we have tested Raspberry Pi 5 official M.2 HAT and Seeed Studio Dual M.2 HAT, both working successfully. We know of more users succesfully testing other HATs.
Hello @dev.manek ,
Did you follow the guide in https://www.waveshare.com/wiki/PCIe_TO_M.2_HAT+ ?
Specifically this is very important:
1: Enable PCIe Interface:
The PCIe interface is not enabled by default on PI5B. To enable it, add the following configuration in /boot/firmware/config.txt:dtparam=pciex1
2: PCIE is gen2 by default, if you need to enable PCIE gen3, add it in /boot/firmware/config.txt:
dtparam=pciex1_gen=3
At the moment, we have tested Raspberry Pi 5 official M.2 HAT and Seeed Studio Dual M.2 HAT, both working successfully. We know of more users succesfully testing other HATs.
Thank you for the reply I will try it with the seed hat and update you
Is your RPi5 set to PCIe Gen3, @dev.manek?
dtparam=pciex1_gen=3
Is your RPi5 set to PCIe Gen3, @dev.manek?
dtparam=pciex1_gen=3
Yes I did. I can confirm that it works with seed dual m.2 hat. But still no stream.
WARNING : Failed to get OpenCL platforms : clGetPlatformIDs failed: PLATFORM_NOT_FOUND_KHR
EDIT:- I am dumb I had no display on. Everything works. Thank you so much guys.
Is your RPi5 set to PCIe Gen3, @dev.manek?
dtparam=pciex1_gen=3
Yes I did. I can confirm that it works with seed dual m.2 hat. But still no stream.
WARNING : Failed to get OpenCL platforms : clGetPlatformIDs failed: PLATFORM_NOT_FOUND_KHR
EDIT:- I am dumb I had no display on. Everything works. Thank you so much guys.
Ah nice work! It’s easy to overlook these things Just glad it’s up and running!
What’s the project you’re building with it @dev.manek?
