Hi all,

I am trying to compile a high-resolution model (1504×1504) on a Metis PCIe card, but the compilation fails due to a memory constraint:

ERROR   : RuntimeError: Could not find a tiling factor that fits the memory constraints l1_constraint=4011520 l2_constraint=7894528. After attempt=7 and h_size=1 and adj_factor=1, memory usage still is memory_usage={L1: {190: 141376, 193: 5017600, 191: 143360}} and per-pool memory usage {L1: 5302336}.

The error indicates a required L1 size (≈5.3 MiB) exceeds the constraint (≈4.0 MiB).

My questions are:

1. Voyager SDK Solution: Is there a Voyager SDK flag or setting to adjust the tiling to overcome this ≈4 MiB L1 limit?

2. Hardware Solution: Are there any Metis card variants (or multi-AIPU cards) that feature a larger per-core L1 cache?

Any guidance on compiling this high-resolution model is appreciated. Thank you!