I propose building an ultra-low-power, deterministic hardware accelerator engine for Edge AI using the Septenary Unitary Conversion (SUC) framework and Base-7 logic on the Metis PCIe platform.
WHAT WE ARE BUILDING:
1. SUC-RNS Core: A parallel combinational Adder-Tree architecture that converts raw data streams into 3-bit unitary vectors (Modulo-7 residues) without conventional long-form division or multipliers.
2. Hardware Acceleration: Implementing an FPGA/RTL-level SUC module to reduce matrix multiplication latency, dynamic power consumption (up to 83.4% reduction), and carry-propagation delays in Edge AI inference pipelines.
3. Voyager SDK & Wingman Integration: Mapping the SUC mathematical reduction layer into Metis hardware via Voyager Wingman for fast pipeline compilation and real-time validation.
FEASIBILITY & DELIVERABLE:
The mathematical foundation and synthesizable Verilog RTL code for 8-bit, 32-bit, and 64-bit buses are already fully designed, validated, and documented. With the Metis PCIe card and Voyager Wingman, I can deploy and benchmark this hardware-efficient SUC pipeline within the 1-month build period.
AUTHOR & RESEARCH CREDS:
• Gautam Pal (Independent Researcher & Rishi-Scientist)
• ORCID iD: https://orcid.org/0009-0004-3456-9972
• Project Reference: GP-SN-2026-03-07-MM
• Master Dataset: https://doi.org/10.5281/zenodo.19999820
• GitHub Repository: https://github.com/GautamPal-K7/K7
-Theory-Archive
