Hello Axelera AI Community,
I would like to present a hardware-efficient implementation of the Septenary Unitary Conversion (SUC) framework, realized as a high-speed Modulo-7 residue generator for Residue Number System (RNS) accelerators and error detection in digital architectures.
PAPER OVERVIEW:
Traditional binary arithmetic accelerators in Edge AI suffer from carry-propagation delays and power constraints during large matrix operations. This paper presents an FPGA-synthesizable Combinational Adder-Tree Core that bypasses long-form division, shifting arithmetic reduction into deterministic 3-bit vector operations using Base-7 logic.
TECHNICAL HIGHLIGHTS:
1. Positional Base-7 Mapping: Converts raw binary streams into 3-bit unitary vectors with a 100% lossless theoretical reconstruction proof.
2. Parallel Combinational Adder-Tree Architecture: Exploits cyclic radix-2 properties modulo 7 [2^k mod 7 = 2^(k mod 3) mod 7] to eliminate dividers and multipliers.
3. Synthesizable Verilog RTL: Included scalable 8-bit, 32-bit, and 64-bit synthesizable Verilog modules (0-cycle combinational latency).
4. Performance Benchmarks vs. Standard Radix-2 Dividers:
- 32-Bit Bus: Reduces LUT consumption from 185 to 58 LUTs; lowers dynamic power by 80.2% (14.2 mW -> 2.8 mW).
- 64-Bit Bus: Reduces LUT consumption from 412 to 112 LUTs; lowers dynamic power by 83.4% (32.6 mW -> 5.4 mW).
AUTHOR & PROJECT DETAILS:
• Principal Investigator: Gautam Pal (Independent Researcher & Innovator)
• Affiliation: Santipur, Nadia, West Bengal, India
• ORCID iD: https://orcid.org/0009-0004-3456-9972
• Project Code: GP-SN-2026-03-07-MM
• Master Zenodo Dataset: https://doi.org/10.5281/zenodo.19999820
• GitHub Theory Archive: https://github.com/GautamPal-K7/K7-Theory-Archive
• Research Blog: https://gautampalresearch.blogspot.com
Looking forward to feedback from hardware architects and Edge AI engineers regarding potential deployment with Voyager SDK and Metis PCIe
acceleration pipelines!
